This slide discusses the parity error detection that is available on the shared, message and dedicated C2, C3, L2 and L3 RAM blocks. For every 32-bits within this RAM there is three parity bits: one for the address, one for the upper 16-bits for the data word and the one bit for the lower 16-bits of the data word. These bits are used to determine if there has been a bit flip in any of the bits that they cover looking for odd or even parity to determine if there was a single bit error. The parity detection is a single cycle 32-bit read or write with no performance lost. This performance also applies to the interleaved block accesses. The blocks where the DMA and CPU buses are connected to dedicated RAM blocks (C2, C3, L2 and L3), interleaved RAM accesses allow block reads by the CPU and DMA such that both the CPU and DMA are able to get single cycle 32-bit reads or writes at the same time for performance. At power up, there’s a function called RAM INIT in the Boot ROM code that initializes RAM. This is important because it initializes in such a way that it protects against ECC or parity errors at power up. RAM, data, parity bits and ECC bits will be initialized at power up. When the data is written, the parity and ECC bits will be automatically calculated. The failure response to a parity error is a Non-maskable interrupt (NMI) to the respective CPU and the error that was detected is logged.