Shown here is the information on access protection for the shared memory. Shared memory refers to the eight blocks of RAM that are available to both the M3 and C28. There are four buses connected to the interface of this shared RAM, these include: the C28 CPU, the C28 DMA, the M3 CPU and the M3 DMA. The table shown at the bottom of this slide describes the set of configuration registers that the M3 uses at power up to decide who has the ownership of the shared RAM, that is who has read-write capabilities. If the master system (M3) has read-write capability it could also have execute only capability. If the DMA were to have ownership of that particular memory block, it would have read-write capability. The same would be said for the C28 CPU and DMA. Obviously, the execute only capability is not available for DMA as it does not have the ability to execute code. Using the S0 RAM block as an example, if the M3 gave ownership of the S0 block to the C28 it would designate not only that the C28 has ownership but that it is execute only, for instance. Then, by default, the M3 would have read only capability. If the M3 has ownership, on the other hand, the C28 would have the read only capability. There is an ability for the owner, once determined by the M3, to decide if there is going to be additional protection including: CPU write-protection, fetch protection or DMA protection. Additionally, the M3 has a memory protection unit (MPU) that can actually block access of the M3 to many portions of the shared RAM. As a final note, this RAM, like all RAM on this device, is single cycle read and write for 32-bit access and has parity detection available.