In summary, the Concerto family has many redundant safety features. Discussed in this presentation were two main parts: memory and peripheral verification. On the memory verification side, access protection, parity error detection, Error Correction Code (ECC), Cyclic Redundancy Check (CRC) and register protection were detailed. The peripheral verification aspects that were covered included ADC and PWM verification, communications verification (CAN, SCI and SPI) and missing clock detection logic. Finally, CPU verification documentation will be released by Texas Instruments in the not too distant future.