Shown here is the dedicated memory and the access protection it uses. In these two blocks, used for illustration purposes, there is Error Correcting Code (ECC) and parity. The M3 has access to all of the C blocks and the C28 has access to the L blocks. In the ECC block, the C0/C1 dedicated memory blocks would have the M3 CPU bus connected to it and the L0/L1 blocks would have the C28 CPU bus connected. Similar to that, the parity dedicated memory C2/C3 blocks will have the M3 CPU and DMA buses connected to it and the L2/L3 blocks will have the C28 CPU and DMA buses connected. With the level of reliability that is achieved from ECC protected memory, critical code and variables should run in ECC RAM first followed by less critical code and variables in the parity RAM. CPU write protection is essentially a way to protect accidental writing to RAM. If there is data and code in the RAM that the designer wants to protect from being overwritten, CPU write protection would be enabled. Once enabled, write protection can only be disabled by a reset. At this point the code is secured, the ECC protection provides the reliability for the data that is stored and the CPU write protection protects against accidental overwriting. When the program counter has been corrupted and it attempts to fetch data (opcodes) that are stored in RAM, the owner of that particular dedicated RAM block can enable fetch protection. Fetch protection does not allow any fetches of opcode from the specified RAM location which is an additional level of protection for the stored data. If there is an attempted fetch and the protection is activated there will be an interrupt that will be identified to the CPU which will, in turn, respond in an orderly fashion.