This slide takes a closer look at the memory on Concerto devices. Depicted here, the master system (Cortex-M3) is located at the top and the control system (C28) is located at the bottom, with several blocks of memory available. There are two types of message RAM: M to C (M3 to C28) and C to M (C28 to M3). Each is 2 KB with parity. Message RAM aids in the ability for the M3 to write into memory so the C28 can read it, and vise versa. It should be noted that each side has their respective read/write (RW) and read only (R) sections. Message RAM is an excellent way to exchange data without having to use the shared RAM. For any level of data, for example, some redundant variables and a critical variable, those would be placed in the message RAM from the C28 writing it and the M3 would then read those values and do a supervisory level verification to be sure the control system is operating within expected parameters. Additionally, there is an inter-processor communications (IPC) block for exchanging short messages and commands. As another example, if the M3 has messages on its communications bus and it needs to relay those messages to the C28, like commanded speed or torque, it could be sent via the IPC. This would cause an interrupt to the C28 and sustain this until the messages are received and the data would be stored in the M to C message RAM. Next to the message RAM there is eight blocks of independent shared RAM. Each block can be configured to provide the M3 or C28 to have read/write capability. The individual blocks can not have both M3 and C28 read/write capabilities at the same time, so there is a section out of these eight blocks to assign what CPU should have this ability. At reset and power up the M3 is in control of the system, as it is the master, so one of it’s jobs is to configure the read/write capability for the different RAM blocks. Once configured, these blocks can only be re-configured after reset. Another thing to take note of is that the Data Read, Data Write and Code Bus’s as well as the DMA Bus have access to both the message and shared RAM. This means that code can execute out of any of these RAM blocks and also be exchanging data with the DMA with these RAM blocks at the same time. This applies to both the M3 and C28.