The F28M35x is the first series in the Concerto family.  It includes two on-board CPUs:  the Arm Cortex-M3™ which is the master CPU and a C28xFPU for the control. There are a couple of different clock options available—75/150 MHz, which is 75MHz for the M3 and 150 MHz for the control processor.  100/100 MHz and 60/60 MHz are other options that will be coming to the market. Memory configurations can range from 1 Meg to 512 KB of Flash with 136 KB to 72 KB of RAM. It will be discussed later in this module how the memory is partitioned between the master device and control processor. With regards to safety, the memory has Error-correcting Code (ECC) and parity available along with other safety and security features which will be detailed.  Functional safety documentation is provided with this processor as well. This product will be available in the 144-pin PowerPad QFP and will be automotive qualified. The block diagram, shown here, points out how the system resources are partitioned. This makes it clear that this part is not a dual core block step homogenous CPU, rather it is a truly heterogeneous dual core processor that has fully independent resources for each processor as well as some shared resources between the processors. The M3 and the 28 are to be running completely independent code. They have their own dedicated flash, dedicated RAM and dedicated peripherals. Now, there is some shared RAM between the two processors, the analog is shared but really the 28 control processor is controlling the A to D, the comparators and DACs because those are crucial components as part of the control loop. The M3 has the read capability and visibility and lower priority visibility of the A to D results. The designer could build a safety strategy around having the M3 be able to help supervisory level visibility on the A to D results that the 28 control processor is using as part of this control loop. The power and the clocking for the device are shared between the two CPUs; there is a single power domain. The dedicated flash in RAM for the M3 and the 28 are ECC enabled, on the shared memory there is parity RAM.