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This slide shows an example of clock generation and distribution for a networking application. The NBVSPA015 is used to generate a 200 MHz LVDS clock which is sent to the NB6N14S. The NB6N14S generates 4 copies of the 200 MHz input clock with LVDS levels. Two of the output clocks are distributed to FPGAs, the other two to proprietary ASICs.
PTM Published on: 2014-08-04
