This slide shows a very generic and complete clock tree for a generic telecom application. On the top left is a clock synthesizer that uses an external crystal to generate a single ended clock output. This single ended clock signal is sent to a level translator to convert the single-ended signal to a differential signal while not modifying the frequency. In the middle left is a clock generator that generates a differential clock signal. At the bottom left is a PLL built out of discrete blocks. onsemi has discrete VCOs, discrete Dividers / Prescalers, and discrete Phase Frequency Detectors in its portfolio. These three clock signal are sent to a multiplexer, which distributes one of the clock signals to several outputs. Before the backplane is a complete fanout buffer offering. onsemi has Fanout Buffers with HCSL outputs, LVDS outputs, LVPECL outputs, CML outputs, and single-ended outputs. At the bottom, in the middle is the Pre-emphasis and equalizer devices which typically integrate a fanout buffer. In the top most line card is a skew tuner used to add delay to a clock signal with integrated fanout buffer. In the middle line card is a zero delay buffer which provides copies of an input clock where the phase of the output clock is aligned to the phase of the input clock. Finally in the bottom line card, is a spread spectrum device with integrated fanout buffer which generates modulated copies of the input signal.