Above are a number of screen shots from PowerArchitectTM 4. The left hand graphic is part of what is called the “Power Design” tab. It shows the different input and output voltages and sequencing inputs; T start, T stop, Rise, and Fall. T start and T stop is the delay from the time the signal is given until the action starts. Conditional sequencing can be achieved by properly configuring the GPIOs in the “Digital Design” tab. In the upper right graphic, the Power Good Flag for channels one and two is logically AND’ed to GPIO0. The Enable for channels three and four is assigned to GPIO 1. By tying these two IOs together, the sequencing of channels 3 and 4 become conditional on the successful power up of channels 1 and 2. The lower right graphic shows an example where all outputs are conditionally sequenced, but in order to do that I2C must be disabled. The new XRP7724 has conditional sequencing built in.