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dead-time-slide21

The layout guidelines for addressing the two loops that the designer wants to minimize, are the gate high and LX because those are where the high current traces are going. The boost capacitor and the bypass capacitor for the level shifted high side gate drive, those can be at the power IC. The low side driver, the two traces that need to minimize the loop are the power ground and the gate low signal. On the right hand side shown here some things to do to avoid creating larger loops inside those two traces. To get around an obstacle via up and via back down rather than going around the obstacle, that will result in higher inductances, and poorer performance of the gate drive, and also radiate to where it could couple back to some other signal on the board.

PTM Published on: 2013-09-19