There is also the ability to program the fault performance. Many FPGA’s want to make sure that the I/O voltage and the core voltage come up together and that the IO voltage is always higher, so that parasitic diodes do not turn on and cause damage to the FPGA. That would occur when the IO voltage is lower than the core voltage. If there is a fault on the I/O voltage and it goes to zero, the core voltage would also need to turn off as quickly as possible. What the designer can do in the power design tab of the Power Architect software, shown here on the lower right circle, one can indicate an active shutdown. What that does is it turns on the low side fet and it turns off the high side fet and clamps the output voltage. So for instance if the designer was to accidently apply a high voltage onto another rail, this will help clamp it and help protect the very expensive FPGA or other processor. In this case the designer has indicated if channel one faults, to follow that fault and turn off as well. This scope shot shows channel one, which is 3.3V faulting and the other three rails programmed to follow it on fault, and one can see how quickly the Power XR products respond to that fault condition, everything is turned off and shut down in less than 50 microseconds, some ringing is shown because what has occurred is that when the low side fet was turned on, the current in the inductor will actually reverse and ring somewhat with the output capacitor, depending on the magnitude of that ring, a diode will be added to the output to clamp the amplitude of the negative ring.