Shown here are two plots showing the wait for AVDD to stabilize, and come up. If the designer has just put a voltage divider to VIN, and tied the enable pin to that, the enable pin comes up first and if the input voltage comes up quickly and turns on the enable pin before the 1.8V is up, the signal which causes the reset in the digital subsystem may not occur. The digital system will come up correctly, 99 times out of a 100, but that 1% is where it may not come up correctly and it may load incorrectly, which will result in the output voltages not coming up in the manner that is expected. There may be OVP faults, or overcurrent protection faults if it does not come up correctly.