Looking at the PIF results, the higher values are bad.  From the PIF results shown on this slide it is clear that the two-FET design B is the best, and that the four-FET design A is the worst. In fact, with layout B, a designer can parallel two devices without any loss of di/dt or dv/dt immunity. If the designer puts four devices in parallel, the devices are twice as sensitive as a single device. In practice this means that the circuit with paralleled devices will have a minimum switching transition time that is twice as long as a single device. This may mean that the power losses of the system will be higher. Layout C is almost identical in performance to the best layout, D and E are somewhat worse.