Based on experimental verification design B has proven to be the most effective layout solution for paralleling eGaN FETs. There are several key characteristics of this layout, such as all the gates of the switch are very tightly clustered in the center of the switch structure. The switching current, represented by the blue arrow, is orthogonal with respect to the current direction of the inter- FET source inductance. This inter-FET inductance is shown in the up and down direction in this figure. The distance between the switches of the half bridge are made to coincide with the supply decoupling capacitor. An important aspect for the layout design of parallel connected eGaN FETs is to keep the two most important parasitic inductances, the gate circuit inductance and the commons source inductance to a minimum. Single and double-layer PCB designs are therefore effectively ruled out as options, and designers need to focus on four or more PCB layers in their designs.