Shown on this slide is the turn-on switching event: turn-on induces a voltage across the common source inductance, the magnitude of which is driven by the di/dt in the switch. This voltage opposes the voltage applied to the gate electrode by the gate drive. Immunity to false turn-off requires a high gate driver on-state impedance. Gate circuit elements can ring sufficiently to over-voltage the gate – these can easily be damped by choice of gate resistance but at the cost of slower switching speed. Mismatched turn-on timing between FETs, caused by differences in FET parameters or differences in parasitic elements in the PCB can result in circulating currents in the gate and power loops.