Shown on this slide are some key layout do nots. Do not allow the switching current to flow in the same direction as the inter-FET common source inductance. Do not separate the gates of the FET cluster. This will significantly increase gate circuit inductance and create alternative current paths for high frequency currents to flow and induce voltage into the gate circuit. Do not split gate nodes across the design. This has the same effect as separating the gates. Do not place the upper switch on the one side of the PCB and the lower on the opposite side of the PCB where they are placed over each other as this creates a lot of vias to connect the various nodes and makes Swiss cheese of any means for E and H field shielding. Finally, do not separate the FETs of a switch to accommodate decoupling capacitors. A half bridge design is less tolerant of high source inductance than it is of drain inductance.