The SAM S70/E70 devices embed a multi-port SRAM to optimize the bandwidth and latency. The goal is to increase the overall MCU performance while securing the high-priority latency-critical requests from the peripherals. So here for instance, at Cycle N, the CPU gets priority against DMA access.  Access from the DMA and the caches are generally burst to consecutive addresses to optimize system performance. This can block the access to memory for the length of the burst in a single port memory. The SRAM has four ports to limit memory access conflicts. A consecutive access typical for a burst is on the next port which stalls a conflicting access for a single cycle only. An arbiter prioritizes the access to the memory for each port. The priority 0 to 3, with 3 the highest, is programmed in each master. The CPU has priority 2. Priority 3 should only by used for masters with limited memory access.