Shown here is the Cortex-M7’s memory architecture. The Non-Volatile Memory (NVM) either on-chip or connected to the EBI or QSPI port can benefit from the CPU’s 16KB I+D cache which makes it possible to fetch instructions and data in parallel. It limits NVM accesses to cache misses and lowers power consumption. It only needs Single cycle access for the CPU to cache, thus boosting performance. Next, system SRAM can be accessed by masters without CPU intervention. Finally, Tightly Coupled Memories (TCM) offer single cycle CPU access. It can be accessed by the on-chip master through the CPU AHB slave port and the size of TCM is configurable.