The diagram on this slide shows a trigger source coming in, going across the CIB, and starting the sample-on-hold window. The trigger sources coming from the clock domain of the C28X are typically 150 MHz, and the trigger pulse must be recognized by the clock domain in the analog sub-system, which is typically a divide by four of the C28X clock, 37.5 MHz. It is typical to have some jitter in a system that has different clock domains. What can be seen in the diagram is a start of conversion signal coming from the ePWM module and being recognized on the falling edge of the clock. There will be between nine and fourteen C28X clock cycles before the start of conversion to the ADC occurs, so it will be a couple of ADC clock cycles for that elapsed time. Once synchronized, a pulse will be generated internally to the sample-and-hold section and it will take another two ADC clock cycles before the sample-and-hold starts. The total of the clock cycles is nine to fourteen, plus the two ADC clock cycles, multiplied by four because of the 150 MHz divided by four as shown in this example. The result is a total of seventeen to twenty two C28X PLL system clock cycles from the point the start of conversion trigger pulse was generated to the point where the sample-and-hold window starts. This is not the mid-point of sample-and-hold, this is not the end point, this is actually the beginning point of the sample-and-hold window.