The diagram shown on this slide illustrates the conversion stage. At the end of the sample-and-hold, the system will generate an early interrupt. This is something that was on the Piccolo device and now is available on the Concerto. In the diagram, the C28X clock is shown at the top at 150 MHz typical. Beneath this is the ADC clock, which is typically the C28X clock divided by four, 37.5 MHz is the maximum. Shown in gold is the conversion cycle that takes thirteen ADC clock cycles, plus a couple of cycles to get the result to the ADC register, and then three to four cycles to get it across the CIB interface and into the C28X register. The total conversion time from the end of the sample-and-hold to the point when the result gets into a 28X register, is eighteen to nineteen CIB clock cycles. In the C28X clock domain, that is seventy two to seventy six PLLSYSCLK cycles at 150 MHz. This particular number assumes that the ADC interrupt is being used, an interrupt on the C28X was triggered, the interrupt was responded to and it is prepared and ready to read the result at this time. Knowing that this amount of time is eighteen to nineteen CIBCLK cycles, or 0.51 mS, the maximum sample rate can be calculated for this particular example of a single conversion, single read at 1.96 Msps. This is a good way to get an understanding of exactly how long it takes, from a control system standpoint which is not doing blocks of data, to convert one or two signals triggered from a peripheral and reading the result.