This slide shows the interrupt signals coming from the ADCs to the C28X and Cortex-M3 domains. There are eight interrupt signals that are shared by ADC1 and ADC2, which is very useful. For example, it is possible to have ADC interrupt 1 being just for ADC interrupt ADC1 and ADC interrupt 2 going to ADC2. Another possibility would be to have ADC1 and 2 share a particular interrupt signal, and in that case the ADC1 and ADC2 would trigger at separate times interleaving them and alternating the setting of that flag for the two converters. There is considerable flexibility in being able to have these interrupt signals connected to both ADCs. The signal moves through the CIB and can be used as a trigger source for DMA events for both the C28X and the M3, plus it has the traditional role of triggering the interrupt on the C28X. It can also trigger an interrupt on the Cortex-M3. These interrupts can be used to trigger the M3 to monitor the results of the C28X control system. The designer might want to take advantage of the DMA and the M3 to always keep the most recent results in memory, allowing the operating system on the M3 to monitor the results to verify that they are safe and within the range that is expected. Measurement systems on Concerto include the CIB interrupt-to-interrupt jitter measurement and the CIB trigger-to-interrupt jitter measurement. The delay counter starts based upon the trigger source coming from the 150 MHz clock domain and moves through the CIB. This starts the sample-and-hold on the ADCs. Once the sample-and-hold window is done and, if the early interrupt flag is enabled, it is going to cause the trigger-to-interrupt jitter measurement to end. There is also a jitter measurement of the trigger going from the 15 MHz clock domain to the 37.5 MHz clock domain and across the CIB into the 150 MHz clock domain. The second jitter measurement system is 100% in the 37.5 MHz clock domain, the analog sub-system clock domain. It is measuring the time between two flags being set, for example between an ADC interrupt flag getting set twice.