The clock tree for the analog sub-system is shown on this slide. The main point to remember is that the ADC clock is synchronous to the C28X clock. At reset, there is a default clock divider of eight, resulting in the ADC clock being at whatever the C28x frequency is divided by eight. A typical situation is to have 150 MHz for the C28X and divide that clock by four to get the maximum ADC clock rate of 37.5 MHz. This results in the fastest sample rate possible of 2.885 Msps per ADC. Taking into consideration that there are two ADCs, the best sample rate that can be achieved on the Concerto device is 5.77 Msps. The diagram shows this clock tree in greater detail, with the C28X clock coming in on the right. At reset where it is divided by eight, change this to divide by four to get the 37.5 MHz for the CIB clock. Also, at reset the ADC clock is connected to the on-board 10 MHz oscillator which is typical of a Piccolo device, this can be switched to the CIB clock once it is configured and running. The ADC will then be running on the 37.5 MHz clock.