This slide shows the accessibility to the analog sub-system in detail. In the lower right hand corner there is a table that shows the resources that are on Concerto, the C28X DMA, C28X CPU, M3 DMA and M3 CPU. Notice that the Cortex-M3 resources can only access the ADC results, and can then trigger an ADC conversion. The Cortex-M3 resources are truly a monitoring resource in the analog sub-system, and the C28X, as part of the control system, is truly controlling the analog sub-system. The C28X DMA and C28X CPU can read ADC result registers, control the comparator and DACs, configure the ADC, and also control the GPIOs that are part of this sub-system. Arbitration that is handled by the CIB, and the series of resources that are connected to this bus; the M3, M3 µDMA, C28X read bus, the write bus, and the C28X read/write bus. There is a round-robin arbitration, the same kind used with the memory blocks. In a typical control system, the ADCs are triggered by the C28X peripherals, typically ePWM, at a rate of 50 to 100 µS. The C28X will receive a flag from the ADC indicating that there is a result ready, the C28X will then read the result. This process will occur at the 50 to 100 µS rate and the C28X continues to control the system. In parallel with this, taking advantage of having the dual core system on Concerto, is the Cortex-M3 monitoring the ADC results which could be a safety feature in an application. The M3 can review the ADC results and make sure that they are within the specified range of expectations. Typically this would be at a much slower rate than the control system is at, in the 10s to 100s of mS, depending on the application. It is a great advantage to be able to do that with the same analog sub-system. In the case where the system is being used as a data acquisition system, the C28X DMA can read ADC1 results and write it to the RAM, while the Cortex-M3 DMA can read the results from ADC2 and write those to RAM.