Clock buffers distribute multiple copies or simple derivatives of an input / reference clock. The reference clock can be from a clock generator, XO, or a system clock. Clock buffers scale their input clock from 2 to more than 10 outputs. They may include I2C, SPI, or pin-controlled features like signal level and format translation, voltage level translation, multiplexing, and input frequency division. These features save space and cost by eliminating external components needed for voltage dividers and/or signal level transition circuits. Shown here is a generic block diagram of Skyworks Solutions universal clock buffer. Some of the more popular universal buffers are Si53301 for 6 outputs, Si53302 for 10 outputs and Si53306 for 4 outputs. Some of the clock buffers have multiple banks with different dividers, consolidating the need of using 2 buffers into one. There are also options with multiple inputs to multiple banks, integrating the need of 2 buffers into one.