Shown here is another clock tree example, with jitter cleaning requirement for the 10G PHYs. The 10G PHYs need very low jitter. From the left, there is a need for clocks driving the PHYs to be synchronized to reference clock. At the same time, there is still the need for other clocks to drive the PCIe, CPU, and FPGA; however, these clocks can be free-running. In order to fulfill the system requirements, the conventional approach will need two clock generators and one jitter attenuating clock. On the right is Skyworks Solutions optimized solution. The Si5345 can replace the functions of the three components in the conventional approach, and improve the jitter performance with Skyworks Solutions proprietary technology, the DSPLL and MultiSynth, used in the Si5345. The Si5345 provides one of the best-in-class jitter performances of <100 fs. This optimized solution will save cost, power and board space. Clock trees provide a fundamentally important part of the system and must be optimized for performance, power and cost. Skyworks Solutions comprehensive portfolio applies to all ranges of applications, from the most demanding in performance to the most cost conscious.