In this slide and the next, Skyworks Solutions timing components can provide an optimized clock tree compared to a conventional approach. In this example, the system needs 10 clock frequencies; some different frequencies and some with multiple copies of the same frequencies. The output format is also different, requiring differential LVDS, LVPECL, HSCL and single-ended LVCMOS at the same time. All the clocks can be free-running. The conventional approach is to use two separate clock generators to generate the frequencies for PCIe, CPU, and FPGA/ASIC/Switch. The reason to use two clock generators is because the same clock generator cannot support different output formats. The clock generating the HSCL output cannot support LVDS output. To drive the two 10G PHY and two 1G PHY, two XOs with one buffer on each one are used. The total component count is six. Alternatively, to generate all these different frequencies with different output formats, one can use Skyworks Solutions Si5341. The Si5341 has low jitter, is programmable to any frequency, and clock generator supports up to 10 different outputs. Si5341 is a clock tree on a chip. Total component count for the same system requirement is one. Skyworks Solutions solution not only reduces the number of components needed, it also reduces board space needed for the timing solution without having to compromise performance.