One requirement when using “auto-repeat” mode is that the CPU must be able to process the incoming or outgoing data at least as fast as the DMA is moving it. The Half Buffer Transfer complete interrupt mode can help mitigate the processing crunch by replacing the CPU block interrupt with a half block complete interrupt. That is, this mode lets the CPU know that the buffer is half full, or half empty if it is being read by the DMA controller. For example, if an A/D is being continuously read by the DMA controller, the Half Buffer Transfer complete interrupt would allow the CPU to start to process the buffer before it becomes completely full. Provided it never gets ahead of the DMA writes, this scheme can be used to relax the CPU response time requirements.