The addition of another bus master within an embedded system always introduces new debugging challenges. The PIC33F and PIC24H DMA controller includes some special debug assist registers to improve user visibility foremost during system debug, however, they are user accessible from any mode. There are two pieces of information captured during every DMA data transfer. The first is the address in dual port SRAM of the most recent transfer completed by the DMA controller. The second is the channel number of the most recently active DMA channel. This data can be used to establish what the DMA was doing at, or at some time prior to, the point when the debugger halted execution. The existing user registers within the DMA controller and its channels can be used to establish the state of each channel. The ‘ping-pong’ mode status bit is used to indicate which of the 2 buffers is currently active. It may also find uses in both system debug and user application.