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DMAC-Slide3

This block diagram shows how the DMA integrates into the dsPIC internal architecture. The CPU communicates with conventional SRAM across the data space X-bus, shown in green. It also communicates to port 1 of the new dual port SRAM block across the same X-bus. It talks to the peripherals across a separate peripheral data space bus, shown in blue, which also resides within X data space. The DMA controller communicates with port 2 of the dual port SRAM, and the DMA port of each of the DMA-ready peripherals across a dedicated DMA transfer bus, shown in red. Note that, unlike most others out there, the Microchip 16-bit CPU architecture is capable of a read and a write access within each CPU bus cycle. The DMA timing is the same, such that it can complete the transfer of a byte or word every bus cycle across its dedicated bus. This also guarantees that all DMA transfers are atomic. That is, once the transfer has started, it will complete within the same cycle, irrespective of other channel activity.

PTM Published on: 2011-11-03