In this example, the A to D converter is configured to continuously convert inputs 0 through 3 in sequence 0, 1, 2, 3, 0, 1 etc.. Conventional DMA transfer would move this data into a sequential buffer. Should the algorithm being executed require, for example, an average value from each channel individually, the CPU would have to either sort the data or, more likely, index through it jumping past the unwanted data which would consume more time and code. PIA mode allows the ATD to create a buffer in dual port SRAM for each channel, the length of which would be programmed within the A to D. In our example, each conversion value would be directed to the corresponding buffer in dual port SRAM based on the PIA address provided by the peripheral. The PIA enabled DMA channel would perform the data transfer and keep track of the transfer count, which would be initialized to match the total size of all buffers combined. The user could configure the channel for ‘one-shot’, ‘auto-repeat’ or ‘ping-pong’ mode, depending upon the application.