The CPU and DMA controller may simultaneously read or read/write to any dual port SRAM or DMA-ready peripheral data register. The only constraint is that the CPU and DMA controller should not simultaneously write to the same address. Of course, under normal circumstances this situation should never arise; however, if for some reason it does, then it’ll be detected, flagged for subsequent analysis if needed, and a ‘DMA fault’ trap exception will be initiated. The CPU write will also be allowed to win, though that’s mainly to provide predictable behavior and is otherwise of little practical consequence. It’s also permissible for the DMA controller to write to a location during the same bus cycle that the CPU is reading it, and vice versa. However, it should be noted that the resultant reads will be of the stale data, not the data written during the cycle in question. Also note that this situation is considered normal operation and will not result in any special action being taken.