The DMA controller moves data between peripheral data registers and data space SRAM. Commonly used techniques such as cycle stealing halt the CPU when a higher priority DMA transfer is requested. This may meet the peripheral real-time constraints but makes CPU timing less predictable. The DMA subsystem uses dual-ported memory and register structures that allow the DMA to operate across its own, independent address and data buses without any impact to CPU operation. Both CPU and DMA controller may read and write to addresses within data space without interference, such as CPU stalls, maximizing real-time performance. The DMA controller supports 8 independent channels, each configurable for byte or word transfers, to or from selected peripherals. The list of currently supported peripherals is shown in the slide. Note that each channel is unidirectional, so to read and write to a peripheral using DMA will require the allocation of 2 channels. Should more than one channel receive a request to transfer data, a simple fixed priority scheme, based on channel number, will dictate which channel completes the transfer and which channel, or channels, are left pending. Each channel moves a block of data of up to 1024 elements, after which it interrupts the CPU to indicate that the block is available for processing. What happens next depends upon the channel operation mode, the details of which will be covered later. Each PIC33F or PIC24H contains 2K bytes of DPSRAM, adequate to concurrently support multiple buffers for several peripherals.