When PIA mode is enabled in a peripheral that supports it, a DMA request interrupt from that peripheral will also be accompanied by an address that is presented to the DMA controller. If the DMA channel that responds to the request is also enabled for PIA operation, it will logically OR the buffer base address with the zero extended incoming PIA address to create the actual dual port SRAM address. The peripheral will determine how many least significant address bits it will control. All the user must do is select a base address for the buffer in dual port SRAM, and ensure that the corresponding number of least significant bits of that address is zero. The DMA channel continues to control the actual data movement, and keeps track of the transfer count. Obviously, the transfer count must be initialized to a value that makes sense for the PIA address sequence generated by the peripheral. Note, that if the channel is not configured for PIA operation, the incoming address is ignored and the data transfer occurs as normal.