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PSoC 4 BLE Low Power Wireless Systems Slide 14

This slide compares the PSoC 4 BLE solution against some of the competition. As can be seen, the PSoC 4 BLE leads all of the competitive solutions spec for spec. It features an ARM Cortex M0 operating at 48 MHz which is the highest performing CPU available among the competitive solutions. The PSoC supports up to 256 kb of flash, when Cypress released the solution it supported 128 kb but shortly after followed with the 256 kb part. The BLE stack consumes 64 kb of the total 256 kb. The Cypress device has the widest operating voltage range, 1.9 to 5.5 volts, and due to combinations of CO communication blocks and UDBs, the PSoC 4 BLE can implement more CO interfaces than the competition. Capacitor sensing, or CapSense, can be accomplished on all of the 36 I/Os on the chip. The Cypress device also features four UDBs, plus it has a 12-bit 1-Msps ADC, four opamps, and two comparators, which is important because these are the programmable analog blocks that allow the user to create AFEs for sensor interfaces. The competitive solutions do not offer such capabilities. PSoC 4 BLE will be available in the QFN and the small chip scale package, or CSP, part offering up to 36 GPIO. When it comes to power consumption the PSoC 4 BLE is very competitive. Shown on the slide is an example of the average current consumption for a one-second connection interval, and for a four second connection interval which is a relaxed BLE spec. Because the Cypress device features the low power modes, deep sleep, hibernate, and stop, they are able to have lower power consumption than the competitors for a four second connection interval. At the same time they are also competitive in the one-second connection interval. Plus, with PSoC 4 BLE the integrated Balun is available which makes it easy to design the RF board layout and save additional cost as well.

PTM Published on: 2015-03-12