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This slide illustrates the safety features of the Hercules Cortex-R4F. The red shows the safety features of the hardware and blue shows the safety features of hardware and software diagnostics, blended. The black areas show non-safety critical modules like JTAG, calibration, debug etc… At the heart of the Hercules Cortex-R4F are the lock-step dual core CPUs. From a programming standpoint there is a single CPU. The second CPU is utilized specifically for monitoring and providing redundancy to the first CPU in lock-step architecture. This MCU has fail safe detection; a core compare module that constantly compares the outputs of both CPUs and if one operates in an unexpected manner it reports back to the hardware error signaling module that has a dedicated pin to the outside world to let the system know that something has critically gone wrong in the core execution of the microcontroller and appropriate action needs to be taken. The physical design of the cores is separate so the gates of the CPU do not intermingle which helps to reduce common cause error. Additionally, there are built-in self-test (BIST) engines inside the device to test the CPU and RAM. These are hardware BISTs that require a small amount of software (a couple registered configs) to be generated to test the CPUs and RAM which are executable either at start up or periodically in the application. Another key point of the architecture is the Error Correction Code (ECC) for the Flash and RAM. The ECC is capable of detecting and correcting single and double bit errors. The logical and physical design of the MCU is optimized to reduce the probability of common cause failure. In other words the way the Flash and RAM are laid out, there are no physical bits adjacent to each other in a single logical word, which provides optimal ECC protection.
