All Ethernet physical layer components require a reference clock, typically 25 MHz ±50 ppm. Commonly this is provided through a 2-pin crystal or CMOS level oscillator as this provides a stable, low jitter reference. However, some applications benefit from using a less stable clock source, such as from an ASIC or FPGA.  The PHYTER architecture is tolerant to relatively high levels of jitter while still meeting the IEEE specified TX jitter and bit error rate limits. The application note referenced contains more details.