SPIFI is more than an interface to storage for data. The Cortex-M CPU can fetch and execute instructions directly from quad SPI flash through this interface. The performance of code execution from serial flash is about 70% of performance from NXP’s internal flash. With LPC4300, for example, the contents of the external flash are addressable in two separate address zones in the memory map. To accommodate today’s serial flash devices, a 128 MB region is reserved in the upper memory above 0x8000 0000. However, in this region it is not possible to use breakpoint debugging due to limitations of Cortex-M. Therefore, a second region is allocated in the lower address space above 0x1400 0000 for debugging purposes. This second window allows up to 64 MB of serial flash contents to be accessed, including breakpoints. This view is a mirror of the lowest 64 MB in the upper address range.