Deep Sleep reduces current to minimum levels by turning off power to most of the chip’s SRAM, and cutting current consumption to 90% less than traditional Sleep mode. While most SRAM does not retain its data when powered-down, there are two general purpose Deep Sleep registers that will remain powered, allowing some context data to be retained. If more data needs to be saved, self-programmed FLASH (or EEPROM memory, if available) is an option. On parts with an internal core voltage regulator, the regulator is shut down during Deep Sleep to conserve power. The voltage regulator needs time to stabilize before the part can wake up from Deep Sleep, therefore Deep Sleep can typically take 1 to 2 milliseconds to exit on these parts. On devices that do not have a core voltage regulator, wake-up times will be much faster, typically 50 µs. Waking up from Deep Sleep causes a Power-On Reset, so execution will resume at the Reset vector rather than at the instructions that follow the sleep instruction. Special Function Registers will reset to their Power-On Reset default values. However, certain registers (such as TRIS) will not affect device behavior until the Deep Sleep “RELEASE” bit is cleared later by software. The RELEASE feature will be discussed later during the firmware overview.