In the microcontroller’s Deep Sleep mode, several processes can remain operating. The RTCC can be configured to keep time during Deep Sleep. It can even continue to output a seconds clock signal. Other I/O pins will maintain their state during Deep Sleep and throughout wake-up until the Deep Sleep “RELEASE” bit is cleared. Deep Sleep registers will retain data over Deep Sleep, even though the rest of SRAM is powered-off. If more data is needed, an application can use the table read/write features to save data to FLASH memory. On some devices, EEPROM memory is also an option. The DSBOR feature can be enabled to provide an indication of integrity for the special Deep Sleep and RTCC registers in case power levels dropped too low for safe operation. In addition to these features, several different wake-up sources can be enabled to operate through Deep Sleep.