The next parameter, the clamping voltage, is one of the most critical parameters for describing the protection offered by the device. Designated as Vc, the clamping voltage is the highest voltage that will appear across the device during a specified surge event. This means that the clamping voltage is the highest voltage that the protected circuit will be exposed to during the test waveform event. The peak pulse current is usually stated in the electrical table alongside the clamping voltage. On most datasheets, the clamping voltage is given for a 1A or 2A waveform that has an 8µS rise time. The clamping voltage would be much higher for an 8000V ESD event with a peak current of 30A because the peak current would be much higher. However, the ESD waveform with it’s sub 1nS rise time can also introduce inductive spikes in the voltage waveform. This often complicates the process of comparing ESD devices so typically clamping voltages are stated with waveforms that remove any distortions due to parasitic test board inductance. Later this presentation will address the added benefit of this technique and how it gives rise to the most important parameter of a protection component which is its dynamic resistance.