Traditional approach of using NAND Flash in the system is to use discrete NAND Flash on the board whereby the host processor communicates directly with the NAND Flash over the NAND Bus Interface. This is called Direct NAND Interface. The approach sounds very intuitive but in reality it has a lot of challenges. The host processor has to perform many functions related to NAND management. It has to do garbage collection which is to free invalid memory space to allow further PROGRAM operations. It has to perform wear levelling which is to implement algorithms to monitor and spread the writes per block in order to prolong the life of the flash. The host needs to do bad block management to improve the reliability and endurance of the flash by mapping bad sectors and avoid storing data in those areas. It also needs to perform error handling along with device mapping. On top of all these, the host processor has to continuously adapt and change according to the NAND Flash die shrinks, which happens quite frequently – because with each shrink NAND Flash block size, page size and ECC requirements might change.