The block diagram on this slide shows the USB 3.0 controller with both USB 2.0 and USB 3.0 PHYs for connecting to USB 2.0 or USB 3.0 hosts. The FIFO protocol management block converts FIFO data to USB packetized data. It also handles two FIFO protocols – multi-channel FT60x mode and a legacy 245 Sync FIFO mode. The internal clock and PLL blocks provide all the necessary clocking for the chip internals, derived from an external 30 MHz clock source on the customer designed PCB. Non-volatile memory (NVM) allows users to customize the device descriptors, enabling the device to appear with the customer's own name when presented to the host PC. Power management controls the power states of the chip such as active or suspend, when the device will go to a lower power state. BCD is the Battery Charger Detection block, another recent extension to the USB specification, first introduced on FTDI solutions with the FT-X series of bridge devices. This block can determine if the USB port is connected to a Standard Downstream Port (SDP) capable of 900 mA and data transfer, a Dedicated Charging Port (DCP), or a Charging Downstream Port (CDP). Depending on the connection, the GPIO lines may control an external switch to control charging currents in a battery operated solution. Dedicated charging ports can supply higher charge currents typically 1.1 A for faster charging.