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The important level shifting and delay-matching characteristics are as follows: 5ns +/-2ns dead-time interval to minimize ‘body diode’ conduction losses: As with silicon, the effective dead-time increases with load as turn-on times increase. Ideally this could be compensated in the gate drive, but is not required. For higher voltage devices this interval is less critical as power levels and the switching period typically increase. +/-2ns propagation delay matching: Propagation delay from input to output for both high-side and low-side need to be matched to a much greater accuracy as determined by the dead-time requirement above. This avoids cross-conduction or shoot-through. The actual delay itself and its variation with temperature are less important. > 50V/ns dV/dt immunity: Switching dV/dt’s of 30V/ns and higher are typical and therefore high dV/dt immunity is required to avoid ‘accidently’ turning on (or off) both power devices due to the dV/dt glitch. For non-synchronous or ‘self driven’ gate drives, level shifting and delay matching is not relevant.
