On this slide we’re showing some examples of the single camera interops. In this case the designer is using a single Tx/Rx port and are either confirming visually or digitally that the signal chain is working. The block diagram and picture on the left, with red box around it and corresponding block diagram above it, demonstrates the use of a Raspberry Pi Camera module V2 that has a Sony iMX219 sensor on it and a Raspberry Pi module to visually confirm the image interconnect is working properly. For this example, the camera is streaming via CSI over the ribbon cable to the Efinix daughter card that is mounted to the receive connector on the evaluation kit.  The design in T20 then decodes and drives that image through the FPGA fabric to the T20 Transmit port with same daughter card and cable connecting to the Raspberry Pi CSI input port, to be shown on the display attached to the Raspberry Pi. Besides the encode and decode of the MIPI/CSI data streams, the FPGA design also has a small image manipulation function that is controlled by push button to prove that the FPGA is actually able to do in line processing of the image. Efinix provides the design files for this example in the Support Center. The other two examples on the right are more simplified interops, without a display. The one on the bottom right is using a camera module and cable from Leopard imaging featuring Sony iMX185 Camera sensor and the other picture on the top right is an example using a On Semi/Omnivision sensor, the OV13850.  In these demo designs, the camera streams are confirmed to be in working order through the Logic and an LED is turned on for confirmation, vs a display being driven.