Common parallel NVM design problems are shown on this slide. First, many systems require a fast nonvolatile memories with high write endurance. Traditional EEPROM or Flash nonvolatile memories have slow write times, above 1 ms, and limited write endurance. Low power asynchronous SRAMS have 45 ns access times but require battery back up to store data on power loss. Second, batteries increase cost, add design complexity, and compromise reliability and RoHS compliance. Battery power management circuits and firmware add cost and complexity and reduce reliability. Coin cell batteries have a limited lifetime which mandates periodic system maintenance and down time. Another problem is the loss of data if the battery charge is drained before the system power is restored. This requires fast time to repair. In addition, batteries contain heavy metals and violate RoHS compliance. NVSRAM helps solve these problems. It provides 20 ns read-write SRAM access time with unlimited endurance, and requires no batteries to retain data on power loss for unlimited periods. Data is reliably stored at power loss without the need for external power management circuits and firmware. Last but not least, NVSRAM fully complies with RoHS requirements.