This slide shows the major points of the implementation of the Cortex®-M3 on the SAM3U in review of the previous slides: the Cortex-M3 Revision 2 is embedded; no implementation of the Wakeup Interrupt Controller; implementation of clock gating to reduce power consumption in low power modes; MPU, the Memory Protection Unit, is embedded; NVIC is implemented, without NMI, providing thirty interrupts and sixteen priority levels; debug level 3 has been implemented; and trace level 1 has been implemented.