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Cortex-M3 Introduction and Specific SAM3U Implementation Slide 19
In summary, the Microchip SAM3U is an ARM® Cortex®-M3 MCU with USB High Speed Device and an integrated transceiver capable of running at up to 96 MHz. General-purpose DMA and distributed SRAM are embedded to sustain high data transfer rates between multiple high-speed peripherals such as the high-speed SDIO, SD/MMC Card, SPI snd 12-bit ADC. The Cortex-M3 core improves code protection and secures multi-application/ task execution. It also features the boot flash bank selection for IAP. There are two bridges on the SAM3U, one for low-speed peripherals with PDC support, and one for high-speed peripherals with DMA support. The two different bridges allow a fetch from the internal SRAM or internal Flash while at the same time performing a transfer from the MMC to and MC card or SD card. There is also a central DMA, a USBHS with its own DMA and PDC and a 5-layer bus matrix used to parallel different transfers and can connect five different masters to up to ten different slaves. There are three different Flash sizes available ranging from 256 kB to 64 kB. Several buffers are also embedded for code and data read optimizations which allow to fetch sequential code at zero wait state, even at full speed 96 MHz. There are three different SRAM sizes on the different versions of the SAM3U ranging from 32 kB to 8 kB. The 4 kB embedded in the NANDFlash Controller can also be used as an SRAM, which means that the 4 kB are in addition to the embedded SRAM in the product. There is a unique 128-bit factory programmed ID for each device. The automatic sleep mode feature is enabled when Flash is accessed at low speed, which ensures that power consumption is reduced.
PTM Published on: 2011-12-27