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Cortex-M3 Introduction and Specific SAM3U Implementation Slide 13
In terms of performance, there are two bridges on the SAM3U, one for slow-speed peripherals with PDC support, and one for high-speed peripherals with DMA support. The two different bridges mean two different slaves on the system, which allows fetch from the internal SRAM or internal Flash while at the same time performing a transfer from the MMC to and MC card or SD card. Other features that ensure the highest bandwidth are the two different SRAM blocks that can be used independently. There is also a central DMA, a USBHS with its own DMA and PDC and a 5-layer bus matrix used to parallel different transfers and can connect five different masters to up to ten different slaves.
PTM Published on: 2011-12-27