The third method is to use hardware accelerators such as DSP blocks, video blocks, and other FPGA IP to clear data bottlenecks. Use this approach of concurrent, or parallel, data co-processing to increase system performance by up to 530x vs. the same Nios® II processor system running custom instructions, which in turn can be 27x faster than executing instructions in software-only mode. During concurrent data co-processing, the CPU starts/stops the co-processor, the co-processor fetches data and stores results, and the CPU runs application code at the same time. This approach is ideal for block data operations like DSP blocks in the FPGA and video acceleration like the VIP suite in an FPGA.