The second method mentioned in the previous slide is to accelerate time-critical software algorithms by adding custom instructions to the embedded processor instruction set. The example shown on this slide is the arithmetic logic unit, or ALU, for Intel®’s Nios® II processor. Using custom instructions, a complex sequence of standard instructions can be reduced to a single, inline instruction implemented in hardware. This feature can be used for a variety of applications to optimize software inner loops for functions, such as digital signal processing, packet header processing, and computation-intensive applications. In this illustration of a 64-kB CRC buffer, the Nios® II configuration wizard provides a GUI used to add up to 256 custom instructions to the Nios® II processor. A custom instruction can accelerate CPU performance by up to 27x faster than software-only operation in a Nios® II processor, as functions like this CRC example run on blocks of data that would be inefficient to run in software-only mode (e.g., cache misses, etc.). Other FPGA-based processor architectures operate on similar principles. The actual performance acceleration may differ from processor to processor architectures and from the custom instruction, or instructions, used.